csc205 Notes.

Posted in csc205 by bnmng on 2011 02/15

Homework, passed out last week.
Read 4.2, 4.3

Given a truth table, translated into a standard two level network.
Basic technique: mark the 1 rows, and ‘and’ them together, then ‘or’ the results.
Product of sums, and of or. Mark the zeros, or them together, then and the results. Need to use parenthesis.

When the xor gate input is 1, it’s an inverter. When it’s a zero, it’s an enabler.
xor – v

from chapter 3. MSB
overflow: add two negs and get a pos, or add two pos and get a negative.

This will be on the test:::
Aibi 00 01 11 10

Cin 0 0 0 1 0

1 0 1 1 1

or of ands.

( c(a+b) ) + ab

(See truth table from handouts)
011 101 110 111
_ _ _
cab cab cab cab

When doing a sum of products, negate the zeros

State Table.

Master slave SR flip flop. Master stores when clock is on, slave stores when clock is off. This prevents feedback errors.

A JK flip flop is an SR flip flop with two and gates, arranged to allow a 1-1 input perform a toggle.

D flip flop. D stands for delay (or data). Only one input (that’s one input plus the clock).

T flop flop. T for toggle.


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